Hardware multithreading & CPU instruction pipelines

Hardware Multithreading &
Low-Level System Performance

A technical journal dedicated to POSIX threads, lock-free concurrency, memory barriers, SIMD vectorization, and CPU cache coherency protocols.

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● atomic_spinlock.c

#include <stdatomic.h>

typedef struct {
    atomic_flag flag;
} spinlock_t;

void spinlock_lock(spinlock_t *lock) {
    // Lock-free spinlock using atomic test-and-set
    while (atomic_flag_test_and_set_explicit(&lock->flag, memory_order_acquire)) {
        /* spin CPU pause */
    }
}

Thread Dispatches

Showing 3 posts

#concurrency 6 min read

Avoiding False Sharing with Cache Line Padding in C++20

How L1/L2 cache line contention invalidates adjacent thread data and how `std::hardware_destructive_interference_size` prevents performance drops.

OCT 2026 Read Dispatch

#atomics 8 min read

Understanding C11 Atomic Memory Orders & Instruction Reordering

Deep dive into `memory_order_relaxed`, `acquire/release` semantics, and sequentially consistent hardware memory barriers across x86 and ARM.

OCT 2026 Read Dispatch

#cache-line 5 min read

Building a High-Performance Lock-Free Ring Buffer Queue

Designing a single-producer single-consumer (SPSC) lock-free ring buffer utilizing atomic memory fences for low latency.

SEP 2026 Read Dispatch

Hardware Multithreading & Low-Level System Performance

Thread Dispatches

Avoiding False Sharing with Cache Line Padding in C++20

Understanding C11 Atomic Memory Orders & Instruction Reordering

Building a High-Performance Lock-Free Ring Buffer Queue

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Hardware Multithreading &
Low-Level System Performance